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| TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L1 Series TMP91CY28 Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, "Points of Note and Restrictions". Especially, take care below cautions. TMP91CY28 CMOS 16-Bit Microcontroller TMP91CY28FG 1. Outline The TMP91CY28 is a high-speed and high-performance 16-bit microcontroller suitable for lowvoltage and low-power applications. The TMP91CY28FG comes in a 100-pin mini flat package. Features of the TMP91CY28FG include the following: (1) High-speed 16-bit CPU (900/L1 CPU) * * * * * Instruction set is upwardly assembly-code compatible. 16-Mbyte linear address space Architecture based on general-purpose registers and register banks 16-bit multiply/divide instructions and bit transfer/arithmetic instructions 4-channel micro DMA (1.6 s/2 bytes at 10 MHz) (2) Minimum instruction execution time: 400 ns (at 10 MHz) (3) 8-Kbyte on-chip RAM 256-Kbyte on-chip ROM (4) External memory expansion * * 16-Mbyte off-chip address space for code and data External bus interface with dynamic bus sizing for 8-bit and 16-bit data ports (5) 4-channel 8-bit timer (6) 2-channel 16-bit timer (7) 4-channel general-purpose serial interface * Both UART and synchronous transfer modes are supported. 030619EBP1 * The information contained herein is subject to change without notice. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. * For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. 91CY28-1 2004-02-10 TMP91CY28 (8) 2-channel serial bus interface * Either I2C mode or clocked-synchronous mode can be selected. (9) 8-channel 10-bit AD converter (with internal sample/hold) (10) Watchdog timer (11) Key wakeup interrupt with 8-bit inputs (12) WAKE output pin (13) BCD adder/subtractor (14) Program patch logic * 6 banks of registers (15) 4-channel chip select/wait controller (16) 48 interrupt sources * * * 9 CPU interrupts: Triggered by software interrupt instruction or upon the execution of an undefined instruction 21 internal interrupts: 7 priority levels 18 external interrupts: 7 priority levels (16 interrupts supporting selection of triggering edge) (17) 80-pin input/output ports (18) Three HALT modes: Programmable IDLE2, IDLE1 and STOP (19) Clock control * Clock gear: Switches the frequency of high-frequency clock within the range from fc to fc/16 1.8 to 2.6 V (fc max 10 MHz) (20) Operating voltage range: VCC (21) Package: P-LQFP100-1414-0.50F 91CY28-2 2004-02-10 TMP91CY28 (P60) SCK0 (P61) SO0/SDA0 (P62) SI0/SCL0 (P63) INT0 (P64) SCOUT (P65) (P66) (P70) TA0IN (P71) TA1OUT Port 6 I2C/SIO (Channel 0) CPU (TLCS-900/L1) XWA XBC XDE XHL XIX XIY XIZ XSP SR High-frequency oscillator X1 X2 EMU0 EMU1 RESET AM0 AM1 ALE AD0 (P00) AD1 (P01) AD2 (P02) AD3 (P03) AD4 (P04) AD5 (P05) AD6 (P06) AD7 (P07) AD8/A8 (P10) AD9/A9 (P11) AD10/A10 (P12) AD11/A11 (P13) AD12/A12 (P14) AD13/A13 (P15) AD14/A14 (P16) AD15/A15 (P17) A0/A16 (P20) A1/A17 (P21) A2/A18 (P22) A3/A19 (P23) A4/A20 (P24) A5/A21 (P25) A6/A22 (P26) A7/A23 (P27) RD (P30) WR (P31) HWR (P32) WAIT (P33) BUSRQ (P34) BUSAK (P35) R/W (P36) (P37) CS0 (P40) CS1 (P41) CS2 (P42) CS3 (P43) AN0/KWI0 (P50) AN1/KWI1 (P51) AN2/KWI2 (P52) AN3/ADTRG/KWI3 (P53) AN4/KWI4 (P54) AN5/KWI5 (P55) AN6/KWI6 (P56) AN7/KWI7 (P57) AVCC AVSS VREFL VREFH 8-bit timer (TMRA0) 8-bit timer (TMRA1) 8-bit timer Port 7 (TMRA2) 8-bit timer (TMRA3) WA BC DE HL IX IY IZ SP 32 bits Clock gear F Port 0 PC (P72) TA3OUT (P73) (P74) (P75) (P80) TB0IN0/INT5 (P81) TB0IN1/INT6 (P82) TB0OUT0 (P83) TB0OUT1 Watchdog timer (WDT) BCD calculator (BCDC) 16-bit timer (TMRB0) Port 8 8-Kbyte RAM Program patch logic 6 banks Port 1 (P84) TB1IN0/INT7 (P85) TB1IN1/INT8 (P86) TB1OUT0 (P87) TB1OUT1 (P90) SCK1 (P91) SO1/SDA1 (P92) SI1/SCL1 (P93) TXD (P94) RXD (P95) SCLK/CTS (P96) (PA0) INT1 (PA1) INT2 (PA2) INT3 (PA3) INT4 (PA4) (PA5) (PA6) (PA7) NMI WAKE DVCC [3] DVSS [3] Port 9 16-bit timer (TMRB1) I2C/SIO (Channel 1) 256-Kbyte ROM Port 2 SIO/UART Port 3 Interrupt controller Port A CS/WAIT controller Port 4 Standby controller (KWI) Port 5 10-bit 8-channel AD converter ( ): Beginning state after reset Figure 1.1 TMP91CY28 Block Diagram 91CY28-3 2004-02-10 TMP91CY28 2. Signal Descriptions This section contains pin assignments for the TMP91CY28 as well as brief descriptions of the TMP91CY28 input and output signals. 2.1 Pin Assignment The following illustrates the TMP91CY28FG pin assignment. 89 DVCC 90 P66 91 DVSS 92 P50/AN0/KWI0 93 P51/AN1/KWI1 94 P52/AN2/KWI2 P53/AN3/ADTRG/KWI3 95 96 P54/AN4/KWI4 97 P55/AN5/KWI5 98 P56/AN6/KWI6 99 P57/AN7/KWI7 100 VREFH 88 87 86 85 84 83 82 81 80 79 78 77 76 P65 P64/SCOUT P63/INT0 P62/SI0/SCL0 P61/SO0/SDA0 P60/SCK0 P43/CS3 P42/CS2 P41/CS1 P40/CS0 P37 P36/R/W P35/BUSAK VREFL AVSS AVCC P70/TA0IN P71/TA1OUT P72/TA3OUT P73 P74 P75 P80/TB0IN0/INT5 P81/TB0IN1/INT6 P82/TB0OUT0 P83/TB0OUT1 P84/TB1IN0/INT7 P85/TB1IN1/INT8 P86/TB1OUT0 P87/TB1OUT1 P90/SCK1 P91/SO1/SDA1 P92/SI1/SCL1 P93/TXD P94/RXD P95/SCLK/CTS AM0 DVCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 TMP91CY28FG Top view LQFP100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P34/BUSRQ P33/WAIT P32/HWR P31/WR P30/RD P27/A7/A23 P26/A6/A22 P25/A5/A21 P24/A4/A20 P23/A3/A19 P22/A2/A18 DVCC NMI DVSS P21/A1/A17 P20/A0/A16 P17/AD15/A15 P16/AD14/A14 P15/AD13/A13 P14/AD12/A12 P13/AD11/A11 P12/AD10/A10 P11/AD9/A9 P10/AD8/A8 P07/AD7 X2 DVSS X1 AM1 RESET P96 WAKE EMU0 EMU1 PA0/INT1 PA1/INT2 PA2/INT3 PA3/INT4 26 27 28 29 30 31 32 33 34 35 36 37 38 50 49 48 47 46 45 44 43 42 41 40 39 P06/AD6 P05/AD5 P04/AD4 P03/AD3 P02/AD2 P01/AD1 P00/AD0 ALE PA7 PA6 PA5 PA4 Figure 2.1.1 100-Pin LQFP Pin Assignment 91CY28-4 2004-02-10 TMP91CY28 2.2 Pin Usage Information Table 2.2.1 to Table 2.2.4 list the input and output pins of the TMP91CY28, including alternate pin names and functions for multi-function pins. Table 2.2.1 Pin Names and Functions (1/4) Pin Name P00 to P07 AD0 to AD7 P10 to P17 AD8 to AD15 A8 to A15 P20 to P27 A0 to A7 A16 to A23 P30 RD Number of Pins 8 I/O I/O I/O I/O I/O Output I/O Output Output Output Output Function Port 0: Individually programmable as input or output Address (Lower): Bits 0 to 7 of the address/data bus Port 1: Individually programmable as input or output Address (Upper): Bits 8 to 15 for address and data bus Address: Bits 8 to 15 of the address bus Port 2: Individually programmable as input or output Address: Bits 0 to 7 of the address bus Address: Bits 16 to 23 of address bus Port 30: Output only Read strobe: Asserted during a read operation from an external memory device. Also asserted during a read from internal memory if P3 8 8 1 P31 WR 1 Output Output I/O Output I/O Input I/O Input I/O Output P32 HWR 1 P33 WAIT 1 P34 BUSRQ 1 P35 BUSAK 1 P36 R/W P37 P40 CS0 1 I/O Output 1 1 I/O I/O Output Note: An external DMA controller configured with the BUSRQ and BUSAK pins cannot access the onchip memory and peripheral function of the TMP91CY28. 91CY28-5 2004-02-10 TMP91CY28 Table 2.2.2 Pin Names and Functions (2/4) Pin Name P41 CS1 Number of Pins 1 I/O I/O Output Function Port 41: Programmable as input or output (with internal pull-up resistor) Chip select 1: Asserted low to enable external devices at programmed addresses. Port 42: Programmable as input or output (with internal pull-up resistor) Chip select 2: Asserted low to enable external devices at programmed addresses. Port 43: Programmable as input or output (with internal pull-up resistor) Chip select 3: Asserted low to enable external devices at programmed addresses. Port 5: Input-only Analog input: Input to the on-chip AD converter AD trigger: Start an AD converter (Multiplexed with P53). Key wakeup input (Multiplexed with P50 to P57) Port 60: Programmable as input or output Clock input/output pin when the serial bus interface 0 is in SIO mode. Port 61: Programmable as input or output (with internal pull-up resistor) Data transmit pin when the serial bus interface 0 is in SIO mode. Data transmit/receive pin when the serial bus interface 0 is in I2C mode; programmable as an open-drain output. Port 62: Programmable as input or output (with internal pull-up resistor) Data receive pin when the serial bus interface 0 is in SIO mode. Clock input/output pin when the serial bus interface 0 is in I2C mode; programmable as an open-drain output. Port 63: Programmable as input or output Interrupt request 0: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive. Port 64: Programmable as input or output System clock output: Drives out fFPH clock. Port 65: Programmable as input or output Port 66: Programmable as input or output Port 70: Programmable as input or output (with internal pull-up resistor) 8-bit timer 0 input: Input to timer 0. Port 71: Programmable as input or output (with internal pull-up resistor) 8-bit timer 1 output: Output from either timer 0 or timer 1. Port 72: Programmable as input or output (with internal pull-up resistor) 8-bit timer 3 output: Output from either timer 2 or timer 3. P42 CS2 1 I/O Output P43 CS3 1 I/O Output P50 to P57 AN0 to AN7 ADTRG 8 KWI0 to KWI7 P60 SCK0 P61 SO0 SDA0 1 Input Input Input Input I/O I/O I/O Output I/O 1 P62 SI0 SCL0 1 I/O Input I/O P63 INT0 1 I/O Input P64 SCOUT P65 P66 P70 TA0IN P71 TA1OUT P72 TA3OUT 1 I/O Output I/O I/O I/O Input I/O Output I/O Output 1 1 1 1 1 91CY28-6 2004-02-10 TMP91CY28 Table 2.2.3 Pin Names and Functions (3/4) Pin Name P73 P74 P75 P80 TB0IN0 INT5 Number of Pins 1 1 1 1 I/O I/O I/O I/O I/O Input Input Function Port 73: Programmable as input or output (with internal pull-up resistor) Port 74: Programmable as input or output (with internal pull-up resistor) Port 75: Programmable as input or output (with internal pull-up resistor) Port 80: Programmable as input or output (with internal pull-up resistor) 16-bit timer 0 input 0: Count/capture trigger input to 16-bit timer 0. Interrupt request 5: Programmable to be rising-edge or falling-edge sensitive. Port 81: Programmable as input or output (with internal pull-up resistor) 16-bit timer 0 input 1: Capture trigger input to 16-bit timer 0. Interrupt request 6: Rising-edge sensitive. Port 82: Programmable as input or output (with internal pull-up resistor) 16-bit timer 0 output 0: Output from 16-bit timer 0. Port 83: Programmable as input or output (with internal pull-up resistor) 16-bit timer 0 output 1: Output from 16-bit timer 0. Port 84: Programmable as input or output (with internal pull-up resistor) 16-bit timer 1 input 0: Count/capture trigger input to 16-bit timer 1. Interrupt request 7: Programmable to be rising-edge or falling-edge sensitive. Port 85: Programmable as input or output (with internal pull-up resistor) 16-bit timer 1 input 1: Capture trigger input to 16-bit timer 1. Interrupt request 8: Rising-edge sensitive. Port 86: Programmable as input or output (with internal pull-up resistor) 16-bit timer 1 output 0: Output from 16-bit timer 1. Port 87: Programmable as input or output (with internal pull-up resistor) 16-bit timer 1 output 1: Output from 16-bit timer 1. Port 90: Programmable as input or output Clock input/output pin when the serial bus interface 1 is in SIO mode. Port 91: Programmable as input or output (with internal pull-up resistor) Data transmit pin when the serial bus interface 1 is in SIO mode. Data transmit/receive pin when the serial bus interface 1 is in I2C mode; programmable as an open-drain output. Port 92: Programmable as input or output (with internal pull-up resistor) Data receive pin when the serial bus interface 1 is in SIO mode. Clock input/output pin when the serial bus interface 1 is in I2C mode; programmable as an open-drain output. Port 93: Programmable as input or output Serial transmit data: Programmable as an open-drain output. P81 TB0IN1 INT6 P82 TB0OUT0 P83 TB0OUT1 P84 TB1IN0 INT7 1 I/O Input Input I/O Output I/O Output I/O Input Input 1 1 1 P85 TB1IN1 INT8 P86 TB1OUT0 P87 TB1OUT1 P90 SCK1 P91 SO1 SDA1 1 I/O Input Input I/O Output I/O Output I/O I/O I/O Output I/O 1 1 1 1 P92 SI1 SCL1 1 I/O Input I/O P93 TXD 1 I/O Output 91CY28-7 2004-02-10 TMP91CY28 Table 2.2.4 Pin Names and Functions (4/4) Pin Name P94 RXD P95 SCLK CTS Number of Pins 1 1 I/O Function I/O Port 94: Programmable as input or output Input Serial receive data I/O Port 95: Programmable as input or output I/O Serial clock input/output Input Serial clear to send I/O Port 96: Programmable as input or output I/O Ports A0 to A3: Individually programmable as input or output (with internal pullup resistor) Input Interrupt request 1 to 4: Individually programmable to be rising-edge or fallingedge sensitive. I/O Ports A4 to A7: Programmable as input or output (with internal pull-up resistor) Output STOP mode monitor This pin drives low when the CPU is operating; the pin is in high-impedance state during reset or in STOP mode. Output Address latch enable (This pin can be disabled in order to reduce noise.) Input Non-maskable interrupt request: Causes an NMI interrupt on the falling edge. Programmable to be rising-edge sensitive. Input Both AM0 and AM1 should be held at logic 1. Output Test pin. This pin should be left open. Output Test pin. This pin should be left open. Input Reset (with internal pull-up resistor): Initializes the whole TMP91CY28. Input Input pin for high reference voltage for the AD converter. Input Input pin for low reference voltage for the AD converter. Power supply pin for the AD converter. Ground pin for the AD converter. I/O Connection pins for an oscillator crystal. Power supply pins. The DVCC pins should be connected to power supply. Ground pins. The DVSS pins should be connected to ground. P96 PA0 to PA3 INT1 to INT4 1 4 PA4 to PA7 WAKE 4 1 ALE NMI 1 1 2 1 1 1 1 1 1 1 2 3 3 AM0 to AM1 EMU0 EMU1 RESET VREFH VREFL AVCC AVSS X1/X2 DVCC DVSS Note: All pins that have built-in pull-up resistors (Other than the RESET pin) can be disconnected from the built-in pull-up resistor by software. 91CY28-8 2004-02-10 TMP91CY28 3. Functional Description This device is a version of expanding its internal mask ROM size to 256 Kbytes. The configuration and the functionality of this device are the same as those of the TMP91CW28. For the functions of this device that are not described here, refer to the TMP91CW28 data sheet. 3.1 Memory Map Figure 3.1.1 shows a memory map of the device in single-chip mode and its memory areas that can be accessed in each addressing mode of the CPU. 000000H Internal I/O (4 Kbytes) 000100H 001000H Direct area (n) Internal RAM (8 Kbytes) 003000H 64-Kbyte area (nn) External memory 010000H 16-Mbyte area (R) (-R) (R+) (R + R8/16) (R + d8/16) (nnn) FC0000H 256 Kbytes internal ROM FFFF00H FFFFFFH Vector table (256 bytes) ( = Internal area) Figure 3.1.1 TMP91CY28 Memory Map (Single chip mode) 91CY28-9 2004-02-10 TMP91CY28 4. Electrical Characteristics 4.1 Maximum Ratings Parameter Supply voltage Input voltage Output current (Per pin) Output current (Per pin) Output current (Total) Output current (Total) Power dissipation (Ta Storage temperature Operating temperature 85C) Soldering temperature (10 s) VCC VIN IOL IOH IOL IOH PD TSOLDER TSTG TOPR Symbol Rating 0.5 to 3.0 0.5 to VCC 2 2 80 80 600 260 55 to 125 20 to 70 0.5 Unit V mA mW C Note: The maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no maximum rating value will ever be exceeded. Point of Note about Solderability of Lead Free Products (Attach "G" to package name) Test Parameter Solderability Test Condition (1) Use of Sn-63Pb solder bath Solder bath temperature = 230C, dipping time = 5 [s] Number of times = One, use of R-type flux (2) Use of Sn-3.0Ag-0.5Cu solder bath Solder bath temperature = 245, dipping time = 5 [s] Number of times = One, use of R-type flux (Use of lead free) Note Pass: Solderability rate until forming 95 % 4.2 DC Electrical Characteristics (1/2) Parameter Symbol VCC 0V VIL VIL1 VIL2 VIL3 VIL4 VIH VIH1 VIH2 VIH3 VIH4 VOL VOH VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC IOL IOH 1.8 to 2.6 V 1.8 to 2.6 V 1.8 to 2.6 V 1.8 to 2.6 V 1.8 to 2.6 V 1.8 to 2.6 V 1.8 to 2.6 V 1.8 to 2.6 V 1.8 to 2.6 V 1.8 to 2.6 V 0.4 mA 200 A VCC VCC 1.8 to 2.6 V 1.8 to 2.6 V 0.8 VCC 0.7 VCC 0.8 VCC 0.85 VCC VCC 0.3 0.15 VCC VCC 0.3 V 0.3 0.2 VCC 0.2 VCC 0.15 VCC 0.3 0.1 VCC V fc Conditions 4 to 10 MHz Min 1.8 Typ. (Note) Max 2.6 Unit V Supply voltage AVCC DVCC AVSS DVSS Low-level input voltage High-level input voltage P00 to P17 (AD0 to AD15) P20 to P37 RESET, NMI, P40 to PA7 AM0 to AM1 X1 P00 to P17 (AD0 to AD15) P20 to P37 RESET, NMI, P40 to PA7 AM0 to AM1 X1 0.9 VCC V Low-level output voltage High-level output voltage Note: VCC 2.0 V, Ta 25C, unless otherwise noted. 91CY28-10 2004-02-10 TMP91CY28 4.2 DC Electrical Characteristics (2/2) Typ. (Note 1) 0.02 0.2 1.8 200 100 0.05 Parameter Input leakage current Output leakage current Power-down voltage (while RAM is being backed up in STOP mode) RESET pull-up resistor Symbol ILI ILO VSTOP 0.0 0.2 VIN VIN Conditions VCC VCC Min Max 5 10 2.6 1000 600 10 Unit A VIL2 0.2 VCC, VIH2 0.8 VCC VCC VCC fc VCC VCC VCC 1.8 to 2.2 V 2.2 to 2.6 V 1 MHz 1.8 to 2.6 V 1.8 to 2.2 V 2.2 to 2.6 V V RRST CIO VTH k pF V Pin capacitance Schmitt width RESET, NMI, P40 to P43, KWI0 to KWI7, P60 to PA7 Programmable pull-up resistor NORMAL (Note 2) IDLE2 IDLE1 STOP 0.3 200 100 0.8 1000 600 2.2 0.7 0.3 0.1 4.0 1.6 0.9 10 RKH k ICC VCC 1.8 to 2.6 V fc 10 MHz (Typ. value VCC 2.0 V) VCC 1.8 to 2.6 V mA A Note 1: VCC 2.0 V, Ta 25C, unless otherwise noted. Note 2: Test conditions for NORMAL ICC: All blocks operating, output pins open, and input pin levels fixed. 91CY28-11 2004-02-10 TMP91CY28 4.3 AC Electrical Characteristics (1) VCC 1.8 to 2.6 V No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Parameter fFPH cycle period (x) A0 to A15 valid to ALE low A0 to A15 hold after ALE low ALE pulse width high ALE low to RD to WR asserted RD negated to ALE high WR negated to ALE high Symbol tFPH tAL tLA tLL tLC tCLR tCLW tACL tACH tCAR tCAW tADL tADH tRD tRR tHR tRAE tWW tDW tWD tAWH tAWL tCW tAPH tAPH2 tAP Equation Min Max 100 0.5x 0.5x x 0.5x 0.5x x x 1.5x 0.5x x 28 35 40 28 20 20 75 70 30 30 3.0x 3.5x 2.0x 2.0x 0 x 1.5x 1.5x x 30 30 70 50 3.5x 3.0x 2.0x 0 3.5x 3.5x 3.5x 170 170 120 100 30 76 82 60 250 fFPH Min 100 22 15 60 22 30 80 25 80 20 70 10 MHz Max Unit ns ns ns ns ns ns ns ns ns ns ns A0 to A15 valid to RD or WR asserted A0 to A23 valid to RD or WR asserted A0 to A23 hold after RD negated A0 to A23 hold after WR negated A0 to A15 valid to D0 to D15 data in A0 to A23 valid to D0 to D15 data in RD asserted to D0 to D15 data in RD width low 224 268 140 170 0 70 120 80 50 230 200 200 180 350 520 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns D0 to D23 hold after RD negated RD negated to next A0 to A23 output WR width low D0 to D15 valid to WR negated D0 to D23 hold after WR negated A0 to A23 valid to WAIT input ((1 N) wait states) A0 to A15 valid to WAIT input ((1 N) wait states) WAIT hold after RD or WR asserted ((1 N) wait states) A0 to A23 valid to port input A0 to A23 valid to port hold A0 to A23 valid to port valid AC measurement conditions Output levels: High 0.7 Input levels: High 0.9 VCC/Low 0.3 VCC/Low 0.1 VCC, CL VCC 50 pF Note: In the table above, the letter x represents the fFPH period, which varies, depending on the programming of the clock gear function. The cycle period of fFPH is half that of the CPU system clock, fSYS. 91CY28-12 2004-02-10 TMP91CY28 (2) Read operation timings tFPH fFPH A0 to A23 CS0 to CS3 R/W tAWH tAWL tCW WAIT tAPH Port input (Note) tADH RD tACL tACH tLC A0 to A15 tAL ALE tLL tRR LA tADL tRR tRD tAPH2 tCAR tRAE tHR D0 to D15 tCLR AD0 to AD15 Note: Since the CPU accesses the internal area to read data from a port, the control signals of external pins such as RD and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 91CY28-13 2004-02-10 TMP91CY28 (3) Write operation timings fFPH A0 to A23 CS0 to CS3 R/W WAIT tAP Port output (Note) WR, HWR AD0 to AD15 A0 to A15 tWW tDW D0 to D15 tCLW ALE tWD tCAW Note: Since the CPU accesses the internal area to write data to a port, the control signals of external pins such as WR and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 91CY28-14 2004-02-10 TMP91CY28 4.4 AD Conversion Characteristics AVCC Parameter Symbol VREFH VREFL VAIN 1 0 IREF (VREFL IREF (VREFL VSS) VLL) VCC VCC VCC 1.8 to 2.6 V 1.8 to 2.6 V 1.8 to 2.6 V VCC, AVSS Max VCC VSS VREFH VSS Unit V Condition VCC VCC 1.8 to 2.6 V 1.8 to 2.6 V Min VCC VSS VREFL Typ. VCC VSS Analog reference voltage ( ) Analog reference voltage ( ) Analog input voltage Analog supply current ADMOD 0.65 0.02 1.0 0.90 5.0 4.0 mA A LSB Total error (Not including quantization error) Note 1: 1LSB (VREFH VREFL)/1024 [V] Note 2: Minimum operating frequency Guaranteed when the frequency of the clock selected whit the clock gear is 4 MHz or higher with fc used. Note 3: The supply current flowing the AVCC pin is included in the digital supply current parameter (ICC). 4.5 SIO Timing (I/O interface mode) Note: In the tables below, the letter x represents the fFPH period, which varies, depending on the programming of the clock gear function. The cycle period of fFPH is half that of the CPU system clock, fSYS. (1) SCLK input mode Parameter SCLK period TXD data to SCLK rise or fall * TXD data hold after SCLK rise or fall * RXD data valid to SCLK rise or fall * RXD data valid after SCLK rise or fall * RXD data valid after SCLK rise or fall * *: Symbol tSCY tOSS tOHS tHSR tSRD tRDS 0 Equation Min 16X tSCY/2 4X 180 (VCC 2 V 10%) tSCY/2 3X 2X 10 tSCY 0 0 Max 10 MHz (Note) Min Max 1.6 220 1000 310 1600 0 Unit s ns ns ns ns ns SCLK rise or fall: Measured relative to the programmed active edge of SCLK. 16X. Note: tSCY 91CY28-15 2004-02-10 TMP91CY28 (2) SCLK output mode Parameter SCLK period TXD data to SCLK rise or fall * TXD data hold after SCLK rise or fall * RXD data valid to SCLK rise or fall * RXD data valid after SCLK rise or fall * RXD data valid after SCLK rise or fall * *: Symbol tSCY tOSS tOHS tHSR tSRD tRDS Equation Min 16X tSCY/2 tSCY/2 0 tSCY 1X 180 1X 180 40 40 Max 8192X 10 MHz Min Max 1.6 760 760 0 1320 280 819 Unit s ns ns ns ns ns SCLK rise or fall: Measured relative to the programmed active edge of SCLK. tSCY SCLK (SCLK output mode/ active-high SCL input mode) SCLK (Active-low SCK input mode) tOSS Transmit data TXD Receive data RXD 0 tOHS 1 tSRD 0 Valid tRDS tHSR 2 3 1 Valid 2 Valid 3 Valid 4.6 Event Counter (TA0IN, TB0IN0, TB0IN1, TB1IN0, TB1IN1) Parameter Clock cycle period Clock low pulse width Clock high pulse width Symbol tVCK tVCKL tVCKH Equation Min Max 8X 4X 4X 100 40 40 10 MHz Min Max 900 440 440 Unit ns ns ns Note: In the tables above, the letter x represents the fFPH period, which varies, depending on the programming of the clock gear function. The cycle period of fFPH is half that of the CPU system clock, fSYS. 91CY28-16 2004-02-10 TMP91CY28 4.7 Interrupts and Timer Capture Note: In the tables below, the letter x represents the fFPH period, which varies, depending on the programming of the clock gear function. The cycle period of fFPH is half that of the CPU system clock, fSYS. (1) NMI and INT0 to INT4 interrupts Parameter Low pulse width for NMI and INT0 to INT4 High pulse width for INT0 to INT4 Symbol tINTAL tINTAL Equation Min Max 4X 4X 40 40 10 MHz Min Max 440 440 Unit ns ns (2) INT5 to INT8 interrupts and capture The input pulse widths for INT5 to INT8 vary with the selected system clock and prescaler clock. The following table shows the pulse widths for different operation clocks: tINTBL (INT5 to INT8 low-level pulse width) Equation Min 8X 128Xc 100 0.1 fFPH 10 MHz Selected Prescaler Clock 00 (fFPH) 10 (fc/16) tINTBH (INT5 to INT8 high-level pulse width) Equation Min 8X 128Xc 100 0.1 fFPH 10 MHz Unit Min 900 12.9 Min 900 12.9 ns s Note: Xc indicates the period of the high-speed oscillator clock (fc). 4.8 SCOUT Pin Parameter High-level pulse width Low-level pulse width Symbol tSCH tSCL Equation Min 0.5T 0.5T 25 25 10 MHz Min 25 25 Max Max Condition VCC VCC 1.8 to 2.6 V 1.8 to 2.6 V Unit ns ns Note: In the table above, the letter T represents the cycle period of the SCOUT output clock. Measurement condition * Output levels: High 0.7 VCC/Low 0.3 VCC, CL 10 pF tSCH SCOUT tSCL 91CY28-17 2004-02-10 TMP91CY28 4.9 Bus Request/Bus Acknowledge BUSRQ (Note 1) BUSAK tCBAL (Note 2) AD0 to AD15 A0 to A23, RD, WR CS0 to CS3, R/W, HWR ALE tABA tBAA (Note 2) Parameter Bus float to BUSAK asserted Bus float after BUSAK negated Symbol tABA tBAA Equation Min 0 0 fFPH Min 0 0 10 MHz Max 300 300 Max 300 300 Condition VCC VCC 1.8 to 2.6 V 1.8 to 2.6 V Unit ns ns Note 1: If the current bus cycle has not terminated due to wait-state insertion, the TMP91CY28 does not respond to BUSRQ until the wait state ends. Note 2: This broken line indicate that output buffers are disabled, not that the signals are at indeterminate states. The pin holds the last logic value present at that pin before the bus is relinquished. This is dynamically accomplished through external load capacitances. The equipment manufacturer may maintain the bus at a predefined state by means of off-chip resistors, but he or she should design, considering the time (Determined by the CR constant) it takes for a signal to reach a desired state. The on-chip, integrated programmable pull-up/ pull-down resistors remain active, depending on internal signal states. 91CY28-18 2004-02-10 TMP91CY28 4.10 Recommended Oscillator Circuit The TMP91CY28 is evaluated by the following resonator manufacturer. The results of evaluation are shown below. Note: The additional capacitance of the resonator connecting pins are the sum of load capacitance C1, C2 and the stray capacitance on the target board. Even when recommended constants for C1 and C2 are used, actual load capacitance may vary with the board, possibly resulting in the malfunction of the oscillator. The board should be designed so that the patterns around the oscillator are as short as possible. Toshiba recommends that the resonator be finally evaluated after it is mounted on the target board. (1) Sample crystal circuit : : 4@ + + Figure 4.10.1 High-frequency Oscillator Connection Diagram (2) Recommended ceramic resonators for the TMP91CY28, manufactured by Murata Manufacturing Co., Ltd. Ta 20 to 70C Oscillating Component Frequency [MHz] 4.0 High-speed oscillator 8.0 10.0 Recommended Resonator CSTCR4M00G55-R0 CSTLS4M00G56-B0 CSTCE8M00G55-R0 CSTLS8M00G56-B0 CSTCE10M0G52-R0 CSTLS10M0G53-B0 Recommended Constants C1 [pF] C2 [pF] Rd [k ] (39) (47) (33) (47) (10) (15) (39) (47) (33) (47) (10) (15) 0 1.8 to 2.6 - VCC [V] Note * * The C1 and C2 constants are enclosed in parentheses for resonator models having built-in capacitors. The product numbers and specifications of the resonators by Murata Manufacturing Co., Ltd. are subject to change. For up-to-date information, please refer to the following URL: http://www.murata.co.jp/search/index.html 91CY28-19 2004-02-10 TMP91CY28 5. Package Dimension P-LQFP100-1414-0.50F Unit: mm 91CY28-20 2004-02-10 |
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